This invention relates to a solid state logical switch having the characteristics of a common emitter device. More particularly, the invention relates to current sourced circuits and utilizes transistor saturation to achieve high capacitance for high transition speed while reducing power requirements of the circuit.
The present invention relates specifically to a large scale integrated circuit (LSI) technology for use in high speed data processing systems and the like. Such systems require logic level translators and specifically, translators employing current switching. The prior art is replete with a host of references defining various logical current switch techniques. Typical examples are current mode switching (CML) and emitter coupled logic (ECL) circuits.
Logic level translators typically utilize current source, current switching and cathode followers to convert diode transistor logic (DTL) and transistor transistor logic (T.sup.2 L) level binary signals into the aforementioned CML and ECL level binary signals. This conversion is used to store and process data which is represented in binary form. Contemporary LSI data processing systems typically employ various types of logic at different portions of the system. In order to transfer data from one portion of the processing system to another, it is often necessary to translate one type of logic signal into the other type of logic signal utilizing signal translators.
These translators use diodes or other semiconductor devices to obtain a fixed voltage drop thereby translating one type of binary signal level into another. Typically, within the prior art, such translators employ a common ground shared by both the input and output signals. In the case of a T.sup.2 L input signal and a CML output signal, the same bus line would be used as a common ground. The T.sup.2 L currents flowing in the common ground bus tend to produce noise signals in the CML output portion of the translator. This is a known disadvantage of those type of switching systems. Moreover, prior art translators tend to produce unequal delays for the positive and negative going voltages of the binary signals when they are translated from T.sup.2 L logic to CML logic. Therefore, an important consideration in current source circuits is to eliminate the noise which is developed to prevent error signals from generating in the output of the data processing system.
Contemporary LSI techniques utilize various current controlled logic gates wherein the circuit design specifically avoids transistor saturation to enable the circuits to have relatively high speed response. Current mode switching has heretofore utilized transistors which are operated out of saturation and with relatively low voltage swing, to maintain high speed operation. The prior art, for example; U.S. Pat. Nos. 3,501,647; 3,523,194, stresses the importance of avoiding transistor saturation in such current mode circuits. When current mode switching circuits are utilized as logic gates, a difference in potential is achieved by applying a relatively high and relatively low binary signal voltage level to one transistor base electrode and a reference voltage to another transistor base electrode. An intermediate value, vis-a-vis the high and low signal levels, is assigned to the reference voltage so that a potential difference exists between the two signal levels. The reference voltage then controls which of the two transistors, generally each having separate collector circuits and a common emitter circuit, is routed through.
In such circuits, with the common emitter circuit coupled to a current source, the logic gate is commonly referred to as a current mode logic (CML) gate. In the typical CML gate, complementary outputs are taken from the collector electrodes of two transistors and each of the complementary outputs is often buffered by a separate emitter-follower transistor. Hence by using a pair of dual emitter-follower transistors, the CML gate exhibits low output impedance and provides signal shift levels so that the output digital voltage level matches the binary input signal.
The benefits of output emitter-follower transistors are well documented, and their principal disadvantage, accounting for the majority of the power dissipation in the CML gate is also well known. Power dissipation in such circuits is broadly recognized as undesirable, but in the context of LSI technology the dissipated heat can especially degrade performance. Prior art attempts to reduce power dissipation such as U.S. Pat. No. 3,549,899 and 3,549,900 use load-current switches so that the emitter current of only one of the dual emitter follower output transistors flows through the common load current path of the gate.
While power dissipation is reduced, the circuit becomes more complicated due to the requirement of additional elements. Accordingly, problems in layout on the chip are increased and penalties in terms of increased chip area and incurred. These problems exist when temperature compensation elements are introduced into the circuit as an alternative to load current switches. However, if computing speed is deemed to be essential, the trade-off of chip area is acceptable. It is well recognized that computing speed, power, and chip area interact and a change in one has an impact on the other two.
Prior art circuits such as U.S. Pat. No. 3,590,274 employ stabilizing circuits to maintain the two different output levels of a CML gate (operating as a NOR) constant over changes in ambient temperature. Such stabilizing circuits recognize power dissipation problems and regulate the output over changes in chip temperature occurring as a result of dissipated heat.
In the known prior art current emitter transistor circuits, operation is maintained outside of saturation. The literature conspicuously avoids driving transistors into saturation given the apparent disadvantages.
A host of references have been considered relative to considering utilizing transistor saturation as a positive aspect of circuit running speed. Within the prior art, it was previously thought that current source saturation resulted in transistor operations out of design specifications and therefore an undesirable technique of circuit operation. The following references are illustrative of a number of prior art current mode logic switching circuits all utilizing transistor operation outside of the saturated regime.
______________________________________ U.S. Pat. No. U.S. Pat. No. ______________________________________ 3,437,831 3,636,384 3,445,680 3,648,061 3,450,896 3,679,917 3,458,719 3,686,512 3,501,647 3,728,560 3,509,363 3,731,120 3,522,446 3,758,791 3,523,194 3,760,190 3,535,546 3,778,646 3,539,824 3,787,737 3,549,899 3,816,758 3,549,900 3,942,033 3,590,274 3,955,099 3,622,799 3,959,666 4,112,314 ______________________________________
IBM Technical Disclosure Bulletin publication entitled "Current Sources" by T. G. Cole et al., Vol. 14, No. 1, June 1971, pages 332-3; PA1 IBM Technical Disclosure Bulletin publication entitled "Emitter-Coupled Logic Circuit" by H. Berger, Vol. 14, No. 5, October 1971, page 1610; and PA1 IBM Technical Disclosure Bulletin publication entitled "Low Power Data-In" by S. J. Park, Vol. 18, No. 10, March 1976, page 3249.
These prior art devices require either junction capacitors or metalization capacitors to achieve bypass resistor techniques. As a result, in the context of a LSI environment, valuable chip area is required to form the necessary capacitance elements. Of the three basic parameters of LSI circuit design, power, speed and chip area, prior art current mode logic devices have tended to maintain power and speed of the system while compromising chip area. This compromise has resulted in increased chip cost. In certain applications cost-performance analysis favors performance, however in commercial areas, cost competitiveness is an essential consideration. As circuit counts increase, sacrifices in chip area become undesirable.
In commercial LSI technology cost is an important criteria in masterslices with circuits having counts in the range of 1500-5000. In such a range, the allowable internal circuit power dissipation is generally in the range of 0.3 to 2.0 mw. At such low power operation, the ability to drive a high capacitance net is a difficult but necessary criteria. The achievement of a current controlled gate operating at low power and at the same speed as conventional current mode switching circuits remains an important area of semiconductor research.